hwtLib.amba.axi_comp.cache package¶
# AXI4 caches This module contains an implementation of various caces for AXI interfaces.
Submodules¶
hwtLib.amba.axi_comp.cache.addrTypeConfig module¶
- class hwtLib.amba.axi_comp.cache.addrTypeConfig.CacheAddrTypeConfig(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
A container of address type configuration and address parsing utils.
- Variables
ADDR_WIDTH – the total width of the address in bits
CACHE_LINE_SIZE – cache line width in bytes
CACHE_LINE_CNT – total number of cache lines available in this cache (sum in all sets/”ways” together).
Address is composed of several parts as shown in table bellow:
tag
index
offset
offset is an offset in cacheline
index is an index of set where the cacheline could be stored in cache
tag is a rest of address used to check if the calenine stored on index in cache is the cacheline of the requested address
hwtLib.amba.axi_comp.cache.cacheWriteAllocWawOnlyWritePropagating module¶
- class hwtLib.amba.axi_comp.cache.cacheWriteAllocWawOnlyWritePropagating.AxiCacheWriteAllocWawOnlyWritePropagating(hdl_name_override: Optional[str] = None)[source]¶
Bases:
CacheAddrTypeConfig
Non-blocking pipelined Set Associative cache for AXI interfaces which is designed to work with an LSU which solves only WAW (write-after-write) conflicts.
The tag_array contains tags and cache line status flags for cache lines.
The lsu_array contains the data for data for pseudo LRU (Last Recently Used) cache replacement policy. It is stored in a separate array due to high requirements for concurrent access which results in increased memory consumption.
The data_array is a RAM where data for cache lines is stored.
The memories are separated because they have a different memory port requirements and we want to keep the number of memory ports and the size of the memory minimal as resource requirements grow exponentially with increasing number of memory ports.
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 16 of type intdata width of interfaces
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
WAY_CNT - default value 2 of type intnumber of places where one cache line can be stored
MAX_BLOCK_DATA_WIDTH - default value 8 of type int
IS_PREINITIALIZED - default value False of type bool
CACHE_LINE_SIZE - default value 2 of type int
CACHE_LINE_CNT - default value 16 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER
read_cancel - of type hwtLib.common_nonstd_interfaces.addr_hs.AddrHs - MASTER
- HDL components
tag_array - of type hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArray
lru_array - of type hwtLib.amba.axi_comp.cache.lru_array.AxiCacheLruArray
data_array - of type hwtLib.mem.ramTransactional.RamTransactional
gen_addr_reg_0 - of type hwtLib.handshaked.reg.HandshakedReg
gen_data_arr_read_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
gen_join_gen_join_join_0 - of type hwtLib.amba.axis_comp.joinPrioritized.AxiSJoinPrioritized
victim_load_status0 - of type hwtLib.handshaked.reg.HandshakedReg
gen_w_fifo_0 - of type hwtLib.amba.axis_comp.fifo.AxiSFifo
- _impl()[source]¶
Read operation:
Use index to lookup in tag memory
if tag matches return cacheline else dispatch read request (the transaction is dispatched with original id, upon data receive the transaction is passed to master without any synchronization with the cache )
Write operation:
Use index to lookup in tag memory
If tag matches and the cacheline is not being replaced update the data in data array.
If tag is not found in corresponding set select a victim and read it from data array, flush it and write back cacheline to array and update tag
- flush_handler(flush_data: TransRamHsW, axi_m_aw: Axi4_addr, axi_m_w: Axi4_w, axi_m_b: Axi4_b)[source]¶
- incr_lru_on_hit(lru_incr: IndexWayHs, tag_res: AxiCacheTagArrayLookupResIntf)[source]¶
- read_handler(ar_tagRes: AxiCacheTagArrayLookupResIntf, axi_s_r: Axi4_r, ar_lru_incr: IndexWayHs, da_r: TransRamHsR, axi_m_ar: Axi4_addr, axi_m_r: Axi4_r)[source]¶
- Parameters
ar_tagRes – Read request including information from tag_array for given tag.
axi_s_r – Read data requested by ar_tagRes.
ar_lru_incr – Incrementing LRU for given address when tag is found.
da_r – Read interface of data_array used when tag is found.
axi_m_ar – Read address request interface to memory when tag is not found.
axi_m_r – Read data requested by axi_m_ar from memory when tag is not found.
- resolve_victim(st0_o_tag_found: RtlSignal, st0_o_found_way: RtlSignal, st0_o_tags: List[StructIntf], victim_way: Handshaked)[source]¶
- write_handler(aw_tagRes: AxiCacheTagArrayLookupResIntf, axi_s_b: Axi4_b, aw_lru_incr: IndexWayHs, victim_way_req: AddrHs, victim_way_resp: Handshaked, da_w: TransRamHsW, tag_update: AxiCacheTagArrayUpdateIntf, init_in_progress: RtlSignal)[source]¶
- Parameters
aw_tagRes – Write request including in information from tag_array for given tag.
axi_s_b – Response requested by aw_tagRes
aw_lru_incr – Incrementing LRU for given address when tag is found.
victim_way_req – Request victim from LRU array for a specified index, when cache is full.
victim_way_resp – Victim address requested by victim_way_req
da_w – Write interface of data_array to write and initiate flush when cache is full.
tag_update – Tag update interface for newly written data.
hwtLib.amba.axi_comp.cache.lru_array module¶
- class hwtLib.amba.axi_comp.cache.lru_array.AxiCacheLruArray(hdl_name_override: Optional[str] = None)[source]¶
Bases:
CacheAddrTypeConfig
A memory storing Tree-PLRU records with multiple ports. The access using various ports is merged together. The victim_req port also marks the way as lastly used. The set port dissables all discards all pending updates and it is ment to be used for an intialization of the array/cache.
- HDL params
ADDR_WIDTH - default value 32 of type int
CACHE_LINE_SIZE - default value 64 of type int
CACHE_LINE_CNT - default value 4096 of type int
INCR_PORT_CNT - default value 2 of type int
WAY_CNT - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
set - of type hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataHs - SLAVE
incr_0 - of type hwtLib.amba.axi_comp.cache.lru_array.IndexWayHs - SLAVE
incr_1 - of type hwtLib.amba.axi_comp.cache.lru_array.IndexWayHs - SLAVE
victim_req - of type hwtLib.common_nonstd_interfaces.addr_hs.AddrHs - SLAVE
victim_data - of type hwt.interfaces.std.Handshaked - MASTER
- HDL components
lru_mem - of type hwtLib.mem.ramXor.RamXorSingleClock
- class hwtLib.amba.axi_comp.cache.lru_array.IndexWayHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
HandshakeSync
hwtLib.amba.axi_comp.cache.pseudo_lru module¶
- class hwtLib.amba.axi_comp.cache.pseudo_lru.PseudoLru(lru_reg: RtlSignal)[source]¶
Bases:
object
Tree-PLRU, Pseudo Last Recently Used (LRU) algorithm * Often used to select least used value in caches etc.
Example for four-way set associative cache (three bits)
each bit represents one branch point in a binary decision tree; let 1 represent that the left side has been referenced more recently than the right side, and 0 vice-versa
are all 4 lines valid? / yes no, use an invalid line | | | bit_0 == 0? state | replace ref to | next state / \ ------+-------- -------+----------- y n 00x | line_0 line_0 | 11_ / \ 01x | line_1 line_1 | 10_ bit_1 == 0? bit_2 == 0? 1x0 | line_2 line_2 | 0_1 / \ / \ 1x1 | line_3 line_3 | 0_0 y n y n / \ / \ ('x' means ('_' means unchanged) line_0 line_1 line_2 line_3 don't care)
- Note
that there is a 6-bit encoding for true LRU for four-way set associative bit 0: bank[1] more recently used than bank[0] bit 1: bank[2] more recently used than bank[0] bit 2: bank[2] more recently used than bank[1] bit 3: bank[3] more recently used than bank[0] bit 4: bank[3] more recently used than bank[1] bit 5: bank[3] more recently used than bank[2]
- Note
this is not a component in order to make this alg independent on lru reg storage type
- Variables
lru_reg – register with bits which represents binary tree used in pseudo LRU. It uses a common binary tree in array node representation index of left is 2x parent index; index of right is 2x parent index + 1
- _build_node_paths(node_paths: Dict[int, List[RtlSignal]], i: int, prefix: List[RtlSignal])[source]¶
Collect in tree paths for items.
hwtLib.amba.axi_comp.cache.tag_array module¶
- class hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArray(hdl_name_override: Optional[str] = None)[source]¶
Bases:
CacheAddrTypeConfig
Storage of cache tags, cache line state bits (valid/shared/dirty…), pseudo-LRU bits
- HDL params
PORT_CNT - default value 2 of type int
UPDATE_PORT_CNT - default value 1 of type intnumber of ports used for record update
ID_WIDTH - default value 4 of type int
WAY_CNT - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
CACHE_LINE_SIZE - default value 64 of type intsize of cacheline [B]
CACHE_LINE_CNT - default value 4096 of type inta total number of cachelines in this array
MAX_BLOCK_DATA_WIDTH - default value 8 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
lookup_0 - of type hwtLib.common_nonstd_interfaces.addr_hs.AddrHs - SLAVE
lookup_1 - of type hwtLib.common_nonstd_interfaces.addr_hs.AddrHs - SLAVE
lookupRes_0 - of type hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArrayLookupResIntf - MASTER
lookupRes_1 - of type hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArrayLookupResIntf - MASTER
update_0 - of type hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArrayUpdateIntf - SLAVE
- HDL components
tag_mem - of type hwtLib.mem.ram.RamSingleClock
- connect_lookup_port(lookup: AddrHs, tag_mem_port_r: BramPort_withoutClk, lookupRes: AxiCacheTagArrayLookupResIntf, update_tmp: StructIntf)[source]¶
- connect_update_port(update: AxiCacheTagArrayUpdateIntf, tag_mem_port_w: BramPort_withoutClk)[source]¶
- class hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArrayLookupResIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
HandshakeSync
Interface used for r/w logic of cache to return result of search in cache
- HDL params
ID_WIDTH - default value 4 of type int
WAY_CNT - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
TAG_T - default value None of type None
- HDL IO
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
found - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
way - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER the index of way where the tag was found (valid only if found=1)
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
- class hwtLib.amba.axi_comp.cache.tag_array.AxiCacheTagArrayUpdateIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
VldSynced
Interface used to insert or delete records in tag array.
- HDL params
WAY_CNT - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER address to store in tag array
way_en - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
delete - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER If true the record will be deleted form array else new record will be inserted.
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
hwtLib.amba.axi_comp.cache.utils module¶
- class hwtLib.amba.axi_comp.cache.utils.CamWithReadPort(hdl_name_override: Optional[str] = None)[source]¶
Bases:
CamMultiPort
Content addressable memory with a read port which can be used to read cam array by index
- HDL params
KEY_WIDTH - default value 15 of type int
ITEMS - default value 32 of type int
USE_VLD_BIT - default value False of type bool
MATCH_PORT_CNT - default value None of type None
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
match - of type hwt.interfaces.std.Handshaked - SLAVE
out - of type hwt.interfaces.std.Handshaked - MASTER
write - of type hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataHs - SLAVE
read - of type hwtLib.amba.axi_comp.lsu.interfaces.AddrDataIntf - SLAVE