hwtLib.peripheral.usb.usb2 package¶

Submodules¶

hwtLib.peripheral.usb.usb2.device_cdc_vcp module¶

class hwtLib.peripheral.usb.usb2.device_cdc_vcp.Usb2CdcVcp(hdlName: str | None = None)[source]¶

Bases: Usb2DeviceCommon

USB2.0 communication device class virtual com port core (serial/uart over USB)

HDL params:

CLK_FREQ - default value 60000000 of type int
DESCRIPTORS - default value [{ header: { bLength: <HBitsConst u8 18> bDescriptorType: <HBitsConst u8 1> } body: { bcdUSB: <HBitsConst u16 512> bDeviceClass: <HBitsConst u8 2> bDeviceSubClass: <HBitsConst u8 0> bDeviceProtocol: <HBitsConst u8 0> bMaxPacketSize: <HBitsConst u8 64> idVendor: <HBitsConst u16 0> idProduct: <HBitsConst u16 0> bcdDevice: <HBitsConst u16 0> iManufacturer: <HBitsConst u8 0> iProduct: <HBitsConst u8 1> iSerialNumber: <HBitsConst u8 0> bNumConfigurations: <HBitsConst u8 1> } }, { header: { bLength: <HBitsConst u8 9> bDescriptorType: <HBitsConst u8 2> } body: { wTotalLength: <HBitsConst u16 67> bNumInterfaces: <HBitsConst u8 2> bConfigurationValue: <HBitsConst u8 1> iConfiguration: <HBitsConst u8 0> bmAttributes: { reserved0: <HBitsConst b5 0> remoteWakeup: <HBitsConst b1 0> selfPowered: <HBitsConst b1 0> reserved1: <HBitsConst b1 1> } bMaxPower: <HBitsConst u8 250> } }, { header: { bLength: <HBitsConst u8 9> bDescriptorType: <HBitsConst u8 4> } body: { bInterfaceNumber: <HBitsConst u8 0> bAlternateSetting: <HBitsConst u8 0> bNumEndpoints: <HBitsConst u8 1> bInterfaceClass: <HBitsConst u8 2> bInterfaceSubClass: <HBitsConst u8 2> bInterfaceProtocol: <HBitsConst u8 1> iInterface: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 5> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 0> } body: { bcdCDC: <HBitsConst u16 272> } }, { header: { bLength: <HBitsConst u8 5> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 1> } body: { bmCapabilities: { supportHandlesCallManagementItself: <HBitsConst b1 0> supportManagementOverDataClassInterface: <HBitsConst b1 0> reserved0: <HBitsConst b6 0> } bDataInterface: <HBitsConst u8 1> } }, { header: { bLength: <HBitsConst u8 4> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 2> } body: { bmCapabilities: { commFeature: <HBitsConst b1 0> lineCodingAndSerialState: <HBitsConst b1 0> sendBreak: <HBitsConst b1 0> networkConnection: <HBitsConst b1 0> reserved0: <HBitsConst b4 0> } } }, { header: { bLength: <HBitsConst u8 5> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 6> } body: { bMasterInterface: <HBitsConst u8 0> bSlaveInterface: <HArrayConst {0: <HBitsConst u8 1>}> } }, { header: { bLength: <HBitsConst u8 7> bDescriptorType: <HBitsConst u8 5> } body: { bEndpointAddress: <HBitsConst b7 2> bEndpointAddressDir: <HBitsConst b1 1> bmAttributes: { transferType: <HBitsConst b2 3> synchronisationType: <HBitsConst b2 0> usageType: <HBitsConst b2 0> reserved0: <HBitsConst b2 0> } wMaxPacketSize: <HBitsConst u16 8> bInterval: <HBitsConst u8 10> } }, { header: { bLength: <HBitsConst u8 9> bDescriptorType: <HBitsConst u8 4> } body: { bInterfaceNumber: <HBitsConst u8 1> bAlternateSetting: <HBitsConst u8 0> bNumEndpoints: <HBitsConst u8 2> bInterfaceClass: <HBitsConst u8 10> bInterfaceSubClass: <HBitsConst u8 0> bInterfaceProtocol: <HBitsConst u8 0> iInterface: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 7> bDescriptorType: <HBitsConst u8 5> } body: { bEndpointAddress: <HBitsConst b7 1> bEndpointAddressDir: <HBitsConst b1 0> bmAttributes: { transferType: <HBitsConst b2 2> synchronisationType: <HBitsConst b2 0> usageType: <HBitsConst b2 0> reserved0: <HBitsConst b2 0> } wMaxPacketSize: <HBitsConst u16 512> bInterval: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 7> bDescriptorType: <HBitsConst u8 5> } body: { bEndpointAddress: <HBitsConst b7 1> bEndpointAddressDir: <HBitsConst b1 1> bmAttributes: { transferType: <HBitsConst b2 2> synchronisationType: <HBitsConst b2 0> usageType: <HBitsConst b2 0> reserved0: <HBitsConst b2 0> } wMaxPacketSize: <HBitsConst u16 512> bInterval: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 4> bDescriptorType: <HBitsConst u8 3> } body: <HArrayConst {0: <HBitsConst u16 1033>}> }, { header: { bLength: <HBitsConst u8 24> bDescriptorType: <HBitsConst u8 3> } body: <HArrayConst {0: <HBitsConst u8 255>, 1: <HBitsConst u8 254>, 2: <HBitsConst u8 85>, 3: <HBitsConst u8 0>, 4: <HBitsConst u8 115>, 5: <HBitsConst u8 0>, 6: <HBitsConst u8 98>, 7: <HBitsConst u8 0>, 8: <HBitsConst u8 50>, 9: <HBitsConst u8 0>, 10: <HBitsConst u8 67>, 11: <HBitsConst u8 0>, 12: <HBitsConst u8 100>, 13: <HBitsConst u8 0>, 14: <HBitsConst u8 99>, 15: <HBitsConst u8 0>, 16: <HBitsConst u8 86>, 17: <HBitsConst u8 0>, 18: <HBitsConst u8 99>, 19: <HBitsConst u8 0>, 20: <HBitsConst u8 112>, 21: <HBitsConst u8 0>}> }] of type hwtLib.peripheral.usb.descriptors.bundle.UsbDescriptorBundle
PRE_NEGOTIATED_TO - default value None of type None
RX_AGGREGATION_TIMEOUT - default value 512 of type intthe timeout (in clk ticks) for a packing of incoming bytes to a USB packet (the bigger packet equals more USB efficiency)

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
phy - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b - SLAVE
usb_rst - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER
rx - of type hwt.hwIOs.std.HwIODataRdVld - MASTER stream data from host
tx - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE stream data to host

HDL components:

usb_core - of type hwtLib.peripheral.usb.usb2.device_core.Usb2DeviceCore
ep_buffers - of type hwtLib.peripheral.usb.usb2.device_ep_buffers.UsbDeviceEpBuffers
gen_tx_hsToAxi4S_0 - of type hwtLib.handshaked.dataRdVldToAxi4Stream.DataRdVldToAxi4Stream

schematic

__annotations__ = {}¶

decode_setup_request_class(setup: HwIOStruct, ep0_stall: RtlSignal, usb_addr_next: RtlSignal, descriptors: UsbDescriptorBundle, req_bDescriptorType: RtlSignal, req_bDescriptorIndex: RtlSignal, dev_configured: RtlSignal, descr_addr: RtlSignal, ep0_trans_len: RtlSignal)[source]¶

generat_descriptor_rom(descriptors: UsbDescriptorBundle, rst)[source]¶

hwtLib.peripheral.usb.usb2.device_common module¶

class hwtLib.peripheral.usb.usb2.device_common.Usb2DeviceCommon(hdlName: str | None = None)[source]¶

Bases: HwModule

USB2.0 device common parts. This component directly handles the functionality of the EP0 and connects the usb_core to ep_buffers.

Attention:

This is an abstract class, which holds the functionality shared between usb devices. In order to use it it needs to be extended to some specific usb device.

Variables:

usb_core – Handles the USB protocol reset, ping, SOF and handshake messages
ep_buffers – handles the data multiplexing and replaying on errors,

__annotations__ = {}¶

connect_core_and_ep_buffers_common(ep0_stall, ep_buffers: UsbDeviceEpBuffers)[source]¶

connect_ep0_data(ep0, setup_stage, descr_d, ep0_trans_len, actual_packet_split)[source]¶

decode_setup_request(setup: HwIOStruct, ep0_stall: RtlSignal, usb_addr_next: RtlSignal, descriptors: UsbDescriptorBundle, req_bDescriptorType: RtlSignal, req_bDescriptorIndex: RtlSignal, dev_configured: RtlSignal, descr_addr: RtlSignal, ep0_trans_len: RtlSignal)[source]¶

decode_setup_request_class(setup: HwIOStruct, ep0_stall: RtlSignal, usb_addr_next: RtlSignal, descriptors: UsbDescriptorBundle, req_bDescriptorType: RtlSignal, req_bDescriptorIndex: RtlSignal, dev_configured: RtlSignal, descr_addr: RtlSignal, ep0_trans_len: RtlSignal)[source]¶

descriptor_ep0_fsm(descriptors: UsbDescriptorBundle)[source]¶: The Control enpoint (EP0) functionality

descriptor_ep0_fsm_get_descriptor(descr_bundle: UsbDescriptorBundle, setup_wLength: RtlSignal, req_bDescriptorType: RtlSignal, req_bDescriptorIndex: RtlSignal, descr_addr: RtlSignal, ep0_get_len: RtlSignal, ep0_stall: RtlSignal)[source]¶

Get descriptor part of the FSM for EP0 configuration endpoint

Parameters:

req_bDescriptorType – the bDescriptorType from the usb device request
req_bDescriptorIndex – the bDescriptorIndex from the usb device request
descr_addr – read address for current descriptor read
ep0_get_len – size how many descriptor bytes should be read

generat_descriptor_rom(descriptors: UsbDescriptorBundle, rst)[source]¶

load_usb_device_request(rx: Axi4Stream, rst: RtlSignal)[source]¶

Parameters:

rx – the port with incoming data
rst – the usb reset or core reset

hwtLib.peripheral.usb.usb2.device_core module¶

class hwtLib.peripheral.usb.usb2.device_core.Usb2DeviceCore(hdlName: str | None = None)[source]¶

Bases: HwModule

Based on USB descriptors build endpoint statemachines, speed negotiation logic, usb reset logic and transaction logic

Variables:

~.phy – An interface to USB PHY which is connected to host
~.ep – And interface to USB endpoint buffers of this device
~.usb_rst – output of USB reset detector
~.usb_speed – An interface which holds the index of the USB version to note which speed was negotiated.
~.current_usb_addr – An input signal with an address currently assigned for this device.
~.PRE_NEGOTIATED_TO – A parameter for testing purposes which can be used to specify the default state of the link negotiation state

HDL params:

CLK_FREQ - default value 60000000 of type int
DESCRIPTORS - default value [{ header: { bLength: <HBitsConst u8 18> bDescriptorType: <HBitsConst u8 1> } body: { bcdUSB: <HBitsConst u16 512> bDeviceClass: <HBitsConst u8 2> bDeviceSubClass: <HBitsConst u8 0> bDeviceProtocol: <HBitsConst u8 0> bMaxPacketSize: <HBitsConst u8 64> idVendor: <HBitsConst u16 0> idProduct: <HBitsConst u16 0> bcdDevice: <HBitsConst u16 0> iManufacturer: <HBitsConst u8 0> iProduct: <HBitsConst u8 0> iSerialNumber: <HBitsConst u8 0> bNumConfigurations: <HBitsConst u8 1> } }, { header: { bLength: <HBitsConst u8 9> bDescriptorType: <HBitsConst u8 2> } body: { wTotalLength: <HBitsConst u16 67> bNumInterfaces: <HBitsConst u8 2> bConfigurationValue: <HBitsConst u8 1> iConfiguration: <HBitsConst u8 0> bmAttributes: { reserved0: <HBitsConst b5 0> remoteWakeup: <HBitsConst b1 0> selfPowered: <HBitsConst b1 0> reserved1: <HBitsConst b1 1> } bMaxPower: <HBitsConst u8 250> } }, { header: { bLength: <HBitsConst u8 9> bDescriptorType: <HBitsConst u8 4> } body: { bInterfaceNumber: <HBitsConst u8 0> bAlternateSetting: <HBitsConst u8 0> bNumEndpoints: <HBitsConst u8 1> bInterfaceClass: <HBitsConst u8 2> bInterfaceSubClass: <HBitsConst u8 2> bInterfaceProtocol: <HBitsConst u8 1> iInterface: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 5> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 0> } body: { bcdCDC: <HBitsConst u16 272> } }, { header: { bLength: <HBitsConst u8 5> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 1> } body: { bmCapabilities: { supportHandlesCallManagementItself: <HBitsConst b1 0> supportManagementOverDataClassInterface: <HBitsConst b1 0> reserved0: <HBitsConst b6 0> } bDataInterface: <HBitsConst u8 1> } }, { header: { bLength: <HBitsConst u8 4> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 2> } body: { bmCapabilities: { commFeature: <HBitsConst b1 0> lineCodingAndSerialState: <HBitsConst b1 0> sendBreak: <HBitsConst b1 0> networkConnection: <HBitsConst b1 0> reserved0: <HBitsConst b4 0> } } }, { header: { bLength: <HBitsConst u8 5> bDescriptorType: <HBitsConst u8 36> bDescriptorSubtype: <HBitsConst u8 6> } body: { bMasterInterface: <HBitsConst u8 0> bSlaveInterface: <HArrayConst {0: <HBitsConst u8 1>}> } }, { header: { bLength: <HBitsConst u8 7> bDescriptorType: <HBitsConst u8 5> } body: { bEndpointAddress: <HBitsConst b7 2> bEndpointAddressDir: <HBitsConst b1 1> bmAttributes: { transferType: <HBitsConst b2 3> synchronisationType: <HBitsConst b2 0> usageType: <HBitsConst b2 0> reserved0: <HBitsConst b2 0> } wMaxPacketSize: <HBitsConst u16 8> bInterval: <HBitsConst u8 10> } }, { header: { bLength: <HBitsConst u8 9> bDescriptorType: <HBitsConst u8 4> } body: { bInterfaceNumber: <HBitsConst u8 1> bAlternateSetting: <HBitsConst u8 0> bNumEndpoints: <HBitsConst u8 2> bInterfaceClass: <HBitsConst u8 10> bInterfaceSubClass: <HBitsConst u8 0> bInterfaceProtocol: <HBitsConst u8 0> iInterface: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 7> bDescriptorType: <HBitsConst u8 5> } body: { bEndpointAddress: <HBitsConst b7 1> bEndpointAddressDir: <HBitsConst b1 0> bmAttributes: { transferType: <HBitsConst b2 2> synchronisationType: <HBitsConst b2 0> usageType: <HBitsConst b2 0> reserved0: <HBitsConst b2 0> } wMaxPacketSize: <HBitsConst u16 64> bInterval: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 7> bDescriptorType: <HBitsConst u8 5> } body: { bEndpointAddress: <HBitsConst b7 1> bEndpointAddressDir: <HBitsConst b1 1> bmAttributes: { transferType: <HBitsConst b2 2> synchronisationType: <HBitsConst b2 0> usageType: <HBitsConst b2 0> reserved0: <HBitsConst b2 0> } wMaxPacketSize: <HBitsConst u16 64> bInterval: <HBitsConst u8 0> } }, { header: { bLength: <HBitsConst u8 4> bDescriptorType: <HBitsConst u8 3> } body: <HArrayConst {0: <HBitsConst u16 1033>}> }] of type hwtLib.peripheral.usb.descriptors.bundle.UsbDescriptorBundle
PRE_NEGOTIATED_TO - default value None of type None

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
phy - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b - SLAVE
ep - of type hwtLib.peripheral.usb.usb2.device_core_interfaces.UsbEndpointInterface - MASTER
usb_rst - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER
usb_speed - of type hwt.hwIOs.std.HwIODataVld - MASTER
current_usb_addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 7bits> - SLAVE

HDL components:

sie_rx - of type hwtLib.peripheral.usb.usb2.sie_rx.Usb2SieDeviceRxSerial Interface Engine for UTMI rx channel (host->device)
sie_tx - of type hwtLib.peripheral.usb.usb2.sie_tx.Usb2SieDeviceTxSerial Interface Engine for UTMI tx channel (device->host)

schematic

__annotations__ = {}¶

define_endpoint_states(endp: RtlSignal, rst_any: RtlSignal)[source]¶

detect_usb_rst(LineState: RtlSignal, usb_speed: HwIODataVld)[source]¶

ms_to_clock_ticks(t_ms)[source]¶

usb_endpoint_fsm(usb_rst: RtlSignal, chirp_en: RtlSignal, ep_rx: Axi4Stream, ep_tx: Axi4Stream, ep_tx_success: HwIODataVld, ep_rx_stall: RtlSignal, ep_tx_stall: RtlSignal)[source]¶

usb_linerate_negotiation(enable: RtlSignalBase, usb_reset: RtlSignal, utmi: Utmi_8b, usb_speed_o: HwIODataVld)[source]¶

hwtLib.peripheral.usb.usb2.device_core._example_Usb2DeviceCore()[source]¶

hwtLib.peripheral.usb.usb2.device_core_interfaces module¶

class hwtLib.peripheral.usb.usb2.device_core_interfaces.UsbEndpointInterface(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

An interface to transfer data between the USB core and endpont memory/usb function

Variables:

ep – endpoint number
stall – 1 if endpoint is dissabled or request is not supported

HDL params:

HAS_RX - default value True of type bool
HAS_TX - default value True of type bool
DATA_WIDTH - default value 8 of type int

HDL IO:

endp - of type hwt.hwIOs.std.HwIODataVld - UNKNOWN
rx_stall - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
rx - of type hwtLib.amba.axi4s.Axi4Stream - UNKNOWN data from host to device(function)
tx_stall - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
tx - of type hwtLib.amba.axi4s.Axi4Stream - UNKNOWN (Master=IN) data from device(function) to host
tx_success - of type hwt.hwIOs.std.HwIODataVld - UNKNOWN tells the endpoint buffer that previously send packet was successfully transferred and the packet can be deallocated (if tx_sucess.vld & ~tx_sucess.data it means that the packet needs to be re-transmited)

__annotations__ = {}¶

hwtLib.peripheral.usb.usb2.device_ep_buffers module¶

class hwtLib.peripheral.usb.usb2.device_ep_buffers.UsbDeviceEpBuffers(hdlName: str | None = None)[source]¶

Bases: HwModule

USB device endpoint buffers Buffers for the data transfers which are between usb core and usb function.

HDL params:

ENDPOINT_META - default value ([<UsbEndpointMeta EP0 OUT [‘setup’] maxPacketSize:64B>, <UsbEndpointMeta EP0 IN [‘setup’] maxPacketSize:64B>], [<UsbEndpointMeta EP1 OUT [‘setup’] maxPacketSize:64B>, <UsbEndpointMeta EP1 IN [‘setup’] maxPacketSize:64B>], [None, <UsbEndpointMeta EP2 IN [‘setup’] maxPacketSize:8B>]) of type tuple
DATA_WIDTH - default value 8 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
usb_core_io - of type hwtLib.peripheral.usb.usb2.device_core_interfaces.UsbEndpointInterface - SLAVE
ep - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

HDL components:

rx_fifos_1 - of type hwtLib.amba.axis_comp.fifoDrop.Axi4SFifoDrop
tx_fifos_1 - of type hwtLib.amba.axis_comp.fifoCopy.Axi4SFifoCopy
tx_fifos_2 - of type hwtLib.amba.axis_comp.fifoCopy.Axi4SFifoCopy
tx_packet_buffered_fifos_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
tx_packet_buffered_fifos_2 - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}¶

connect_rx_part(rx_channels: List[Tuple[int, Axi4Stream, UsbEndpointMeta, Axi4SFifoDrop]])[source]¶

connect_tx_part(tx_channels: List[Tuple[int, Axi4Stream, UsbEndpointMeta, Axi4SFifoCopy, HandshakedFifo]])[source]¶

hwDeclr() → None[source]¶

Note:: ep.rx = from host, ep.tx = to host

hwtLib.peripheral.usb.usb2.device_ep_buffers._example_UsbDeviceEpBuffers()[source]¶

hwtLib.peripheral.usb.usb2.sie_interfaces module¶

class hwtLib.peripheral.usb.usb2.sie_interfaces.DataErrVldKeepLast(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataVld

HDL params:

DATA_WIDTH - default value 64 of type int
USE_KEEP - default value True of type bool

HDL IO:

data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
keep - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
error - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.usb.usb2.sie_interfaces.DataErrVldKeepLastAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)[source]¶

Bases: HwIODataVldAgent

A simulation agent for DataErrVldKeepLast interface.

__annotations__ = {}¶

get_data()[source]¶

set_data(data)[source]¶

class hwtLib.peripheral.usb.usb2.sie_interfaces.Usb2SieRxOut(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataVld

HDL IO:

pid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
endp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
frame_number - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 11bits> - UNKNOWN
error - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.usb.usb2.sie_interfaces.Usb2SieRxOutAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)[source]¶

Bases: HwIODataVldAgent

A simulation agent for Usb2SieRxOut interface.

__annotations__ = {}¶

get_data()[source]¶

set_data(data)[source]¶

hwtLib.peripheral.usb.usb2.sie_rx module¶

class hwtLib.peripheral.usb.usb2.sie_rx.Usb2SieDeviceRx(hdlName: str | None = None)[source]¶

Bases: HwModule

UTMI rx (host->device) packet parser and CRC checker and cutter, (SIE stands for serial interface engine)

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
enable - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE
rx - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_rx - SLAVE
current_usb_addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 7bits> - SLAVE
rx_header - of type hwtLib.peripheral.usb.usb2.sie_interfaces.Usb2SieRxOut - MASTER
rx_data - of type hwtLib.peripheral.usb.usb2.sie_interfaces.DataErrVldKeepLast - MASTER

HDL components:

parser_pid - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
parser_token - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
parser_payload - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
crc5 - of type hwtLib.logic.crcComb.CrcComb
crc16 - of type hwtLib.logic.crc.Crc
gen_payload_reg_0 - of type hwtLib.amba.axis_comp.reg.Axi4SReg

schematic

_Utmi_8b_rx_to_DataErrVldStrbLast(rx: Utmi_8b_rx)[source]¶

__annotations__ = {}¶

hwtLib.peripheral.usb.usb2.sie_tx module¶

class hwtLib.peripheral.usb.usb2.sie_tx.Usb2SieDeviceTx(hdlName: str | None = None)[source]¶

Bases: HwModule

UTMI Tx packet CRC appender and chirp inserter, (SIE stands for serial interface engine)

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
enable - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE
tx_cmd - of type hwtLib.peripheral.usb.usb2.sie_tx.Usb2SieDeviceTxInput - SLAVE An interface which should be used to control this component
tx - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_tx - MASTER The Tx part of the Utmi_8b interface

HDL components:

deparser_hs - of type hwtLib.amba.axis_comp.frame_deparser._deparser.Axi4S_frameDeparser
deparser_data - of type hwtLib.amba.axis_comp.frame_deparser._deparser.Axi4S_frameDeparser
gen_tx_cmd_reg_0 - of type hwtLib.amba.axis_comp.reg.Axi4SReg
crc16 - of type hwtLib.logic.crc.Crc
gen_join_gen_join_join_0 - of type hwtLib.amba.axis_comp.joinPrioritized.Axi4SJoinPrioritized

schematic

_Axi4Stream_to_Utmi_8b_tx(axis: Axi4Stream, tx: Utmi_8b_tx)[source]¶: Convert last signal to a space between packets

__annotations__ = {}¶

class hwtLib.peripheral.usb.usb2.sie_tx.Usb2SieDeviceTxInput(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: Axi4Stream

HDL params:

IS_BIGENDIAN - default value False of type bool
USE_STRB - default value False of type bool
USE_KEEP - default value True of type bool
ID_WIDTH - default value 0 of type int
DEST_WIDTH - default value 0 of type int
DATA_WIDTH - default value 8 of type int
USER_WIDTH - default value 0 of type int

HDL IO:

pid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
chirp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
keep - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit, force_vector> - UNKNOWN
last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_getIpCoreIntfClass()[source]¶

hwtLib.peripheral.usb.usb2.ulpi module¶

class hwtLib.peripheral.usb.usb2.ulpi.IP_Ulpi[source]¶

Bases: IntfIpMeta

__annotations__ = {}¶

__init__()[source]¶

library¶

name¶

vendor¶

version¶

class hwtLib.peripheral.usb.usb2.ulpi.ULPI_REG[source]¶

Bases: object

Note:: all registers are 8b in size

Carkit_Control = 25¶

Carkit_Interrupt_Delay = 28¶

Carkit_Interrupt_Enable = 29¶

Carkit_Interrupt_Latch = 33¶

Carkit_Interrupt_Status = 32¶

Carkit_Pulse_Control = 34¶

Debug = 21¶

Function_Control = 4¶

Interface_Control = 7¶

OTG_Control = 10¶

Product_ID_High = 3¶

Product_ID_Low = 2¶

REGS_WITH_SET_AND_CLR = [4, 7, 10, 13, 16, 22, 25, 29, 34]¶

Receive_Polarity_Recovery = 39¶

Scratch_Register = 22¶

Transmit_Negative_Width = 38¶

Transmit_Positive_Width = 37¶

USB_Interrupt_Enable_Falling = 16¶

USB_Interrupt_Enable_Rising = 13¶

USB_Interrupt_Latch = 20¶

USB_Interrupt_Status = 19¶

Vendor_ID_High = 1¶

Vendor_ID_Low = 0¶

clr_of(addr)[source]¶: By write to this address the pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero (cleared).

classmethod set_of()[source]¶: By write to this address the pattern on the data bus is OR’d with and written into the register.

class hwtLib.peripheral.usb.usb2.ulpi.ULPI_TX_CMD[source]¶

Bases: object

EXTR = 239¶

EXTW = 175¶

Variables:: REGR – Register read command with 6-bit immediate address.

NOOP = 0¶

Variables:: NOOP – Transmit USB data that does not have a USB_PID, such as chirp and resume signalling. The PHY starts transmitting on the USB beginning with the next data byte.

NOPID = 64¶

static REGR(addr)[source]¶

static REGW(addr)[source]¶: Register write command with 6-bit immediate address.

static USB_PID(pid: USB_PID)[source]¶: Transmit USB packet. data(3:0) indicates USB packet identifier USB_PID(3:0).

static get_USB_PID(packet_first_byte)[source]¶

static is_USB_PID(packet_first_byte)[source]¶

class hwtLib.peripheral.usb.usb2.ulpi.Ulpi(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

ULPI (UTMI+ Low Pin HwIO for USB2.0 PHY)

https://www.sparkfun.com/datasheets/Components/SMD/ULPI_v1_1.pdf

Variables:

~.data – Bi-directional data bus, driven low by the Link during idle. Bus ownership is determined by dir. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. LPI defines interface timing for single-edge data transfers with respect to rising edge of clock. An implementation may optionally define double-edge data transfers with respect to both rising and falling edges of clock.
~.dir – Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives dir high to take ownership of the bus. When the PHY has no data to transfer it drives dir low and monitors the bus for Link activity. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PHY PLL is not stable.
~.stp – Stop. The Link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, stp indicates the last byte of data was on the bus in the previous cycle. If the PHY is sending data to the Link, stp forces the PHY to end its transfer, de-assert dir and relinquish control of the the data bus to the Link. (In the tx stp=1 is asserted after last word, data with stp=1 and after are interpreted as idle (until dir changes).)
~.nxt – Next. The PHY asserts this signal to throttle the data. When the Link is sending data to the PHY, nxt indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. When the PHY is sending data to the Link, nxt indicates when a new byte is available for the Link to consume. (In the rx nxt=0 means the transaction is paused and rx_cmd word is send instead of data.)

HDL params:

DATA_WIDTH - default value 8 of type int

HDL IO:

data - of type hwt.hwIOs.hwIOTristate.HwIOTristateSig - UNKNOWN (Master=IN)
dir - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
stp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
nxt - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

class DIR[source]¶

Bases: object

Note:: if dir == PHY the data flows to PHY

LINK = 0¶

PHY = 1¶

__annotations__ = {}¶

_getIpCoreIntfClass()[source]¶

_initSimAgent(sim: HdlSimulator)[source]¶

hwtLib.peripheral.usb.usb2.ulpi_agent module¶

class hwtLib.peripheral.usb.usb2.ulpi_agent.UlpiAgent(sim: HdlSimulator, hwIO: Ulpi, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Agent for hwtLib.peripheral.usb.usb2.ulpi.Ulpi interface. It allows for receiving and transmitting raw data over ULPI, it does not implement USB stack.

Note:: the RX is always from PHY to Link, the TX is always from Link to PHY
Note:: in link->phy nxt works as a handshake ready and stp as handshake valid_n and data is data.o

:note in phy->link nxt works as a handshake valid (but when set to 0 rx_cmd is send instead of data): and the stp works as handshake ready_n, if stp is set to 1 the transmission of whole packet is interrupted.

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO: Ulpi, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

build_RX_CMD()[source]¶

data_read()[source]¶

driver()[source]¶

Drive ULPI interface as a PHY (and host) does

Inputs:

data.t (should be 0 in rx and turnaround else mask(8))

data.o (only in tx, 1st byt is cmd, rest is data)

stp (1 for 1 clk after last word in tx)

Outputs:

data.i (None in tx, else depending on nxt)

dir

nxt (0 if tx should stall or rx is stalled and sending rxd cmd instead)

monitor()[source]¶

Emulate behavior of the link (and device)

Inputs:

data.i

dir

nxt

Outputs:

data.t

data.o

stp

on_link_to_phy_packet(packet: list)[source]¶

on_phy_to_link_packet(packet: list)[source]¶

parse_RX_CMD(ulpi_data: int)[source]¶

hwtLib.peripheral.usb.usb2.ulpi_usb_agent module¶

class hwtLib.peripheral.usb.usb2.ulpi_usb_agent.UlpiUsbAgent(sim: HdlSimulator, hwIO: Ulpi, allowNoReset=False)[source]¶

Bases: UlpiAgent

hwtLib.peripheral.usb.usb2.ulpi_agent.UlpiAgent with device host logic and USB stack

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO: Ulpi, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶

Drive ULPI interface as a PHY (and host) does

Inputs:

data.t (should be 0 in rx and turnaround else mask(8))

data.o (only in tx, 1st byt is cmd, rest is data)

stp (1 for 1 clk after last word in tx)

Outputs:

data.i (None in tx, else depending on nxt)

dir

nxt (0 if tx should stall or rx is stalled and sending rxd cmd instead)

getDrivers()[source]¶

Note:: use only before running simulator

getMonitors()[source]¶

Note:: use only before running simulator

monitor()[source]¶

Emulate behavior of the link (and device)

Inputs:

data.i

dir

nxt

Outputs:

data.t

data.o

stp

run_usb_driver()[source]¶

class hwtLib.peripheral.usb.usb2.ulpi_usb_agent.UlpiUsbDevProcAgent(rx: Deque[UsbPacketToken | UsbPacketData], tx: Deque[UsbPacketToken | UsbPacketData], descriptors: UsbDescriptorBundle)[source]¶

Bases: UsbDevAgent

__annotations__ = {}¶

deparse_packet(p: UsbPacketToken | UsbPacketData | UsbPacketHandshake)[source]¶: Called to convert the packet from types supported by this class before putting into tx/rx queue

parse_packet(p: Deque[int])[source]¶: Called to convert the packet from tx/rx queues to types supported by this class

parse_packet_pid_and_bytes(pid: int, p: Deque[int])[source]¶

class hwtLib.peripheral.usb.usb2.ulpi_usb_agent.UlpiUsbHostProcAgent(rx: Deque[UsbPacketToken | UsbPacketData | UsbPacketHandshake], tx: Deque[UsbPacketToken | UsbPacketData | UsbPacketHandshake])[source]¶

Bases: UtmiUsbHostProcAgent

A simulation agent for hwtLib.peripheral.usb.usb2.ulpi.Ulpi interface with the functionality of the host.

__annotations__ = {}¶

deparse_packet(p: UsbPacketToken | UsbPacketData | UsbPacketHandshake)[source]¶: Called to convert the packet from types supported by this class before putting into tx/rx queue

parse_packet(p: Deque[int])[source]¶: Called to convert the packet from tx/rx queues to types supported by this class

hwtLib.peripheral.usb.usb2.utmi module¶

class hwtLib.peripheral.usb.usb2.utmi.Utmi_8b(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

UTMI+ (USB 2.0 Transceiver Macrocell Interace) Level 3, 8b variant only

https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specification.pdf http://ww1.microchip.com/downloads/en/DeviceDoc/00002142A.pdf

HDL IO:

LineState - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN
function_control - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 2bits> XcvrSelect <HBits, 1bit> TermSelect <HBits, 2bits> OpMode <HBits, 1bit> Reset <HBits, 1bit, n> SuspendM //<HBits, 1bit> empty space } - UNKNOWN (Master=IN)
otg_control - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 1bit> IdPullup <HBits, 1bit> DpPulldown <HBits, 1bit> DmPulldown <HBits, 1bit> DischrgVbus <HBits, 1bit> ChrgVbus <HBits, 1bit> DrvVbus <HBits, 1bit> DrvVbusExternal <HBits, 1bit> UseExternalVbusIndicator } - UNKNOWN (Master=IN)
interrupt - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 1bit> HostDisconnect <HBits, 1bit> VbusValid <HBits, 1bit> SessValid <HBits, 1bit> SessEnd <HBits, 1bit> IdGnd //<HBits, 3bits> empty space } - UNKNOWN
tx - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_tx - UNKNOWN (Master=IN)
rx - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_rx - UNKNOWN

class LINE_STATE_BIT[source]¶

Bases: object

DM = 1¶

DP = 0¶

class OP_MODE[source]¶

Bases: object

DISABLE_BIT_STUFFING_AND_NRZI = 2¶

NON_DRIVING = 1¶

NORMAL = 0¶

class TERM_SELECT[source]¶

Bases: object

FS = 1¶

HS = 0¶

class XCVR_SELECT[source]¶

Bases: object

FS = 1¶

HS = 0¶

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_rx(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataVld

HDL params:

DATA_WIDTH - default value 8 of type int

HDL IO:

data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
active - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
error - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_tx(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataRdVld

HDL params:

DATA_WIDTH - default value 8 of type int

HDL IO:

data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

hwtLib.peripheral.usb.usb2.utmi_agent module¶

class hwtLib.peripheral.usb.usb2.utmi_agent.Utmi_8bAgent(sim: HdlSimulator, hwIO: Utmi_8b)[source]¶

Bases: AgentBase

Simulation agent for hwtLib.peripheral.usb.usb2.utmi.Utmi_8b interface.

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO: Utmi_8b)[source]¶

property actual_link_to_phy_packet¶

property actual_link_to_phy_packet_setter¶

property actual_phy_to_link_packet¶

property actual_phy_to_link_packet_setter¶

driver()[source]¶: Implement this method to drive your interface in simulation/verification

getDrivers()[source]¶: Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]¶: Called before simulation to collect all monitors of interfaces from this agent

property link_to_phy_packets¶

property link_to_phy_packets_setter¶

monitor()[source]¶: Implement this method to monitor your interface in simulation/verification

property phy_to_link_packets¶

property phy_to_link_packets_setter¶

class hwtLib.peripheral.usb.usb2.utmi_agent.Utmi_8b_rxAgent(sim: HdlSimulator, hwIO: Utmi_8b_rx, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Simulation agent for hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_rx interface.

Attention:: “active” signal acts as a valid, “valid” signal acts as a mask
Variables:: data – Deque[Deque[Tuple[int, int]]] (internal deque represents packets, tuple represents data, error)

USB_ERROR = 'ERROR'¶

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO: Utmi_8b_rx, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶: Implement this method to drive your interface in simulation/verification

get_data()[source]¶

monitor()[source]¶: Implement this method to monitor your interface in simulation/verification

set_active(val)[source]¶

set_data(data)[source]¶

class hwtLib.peripheral.usb.usb2.utmi_agent.Utmi_8b_txAgent(sim: HdlSimulator, hwIO, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Simulation agent for hwtLib.peripheral.usb.usb2.utmi.Utmi_8b_tx interface.

Variables:: data – Deque[Deque[int]] (internal deque represents packets)

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶: Implement this method to drive your interface in simulation/verification

monitor()[source]¶: Implement this method to monitor your interface in simulation/verification

hwtLib.peripheral.usb.usb2.utmi_to_ulpi module¶

class hwtLib.peripheral.usb.usb2.utmi_to_ulpi.Utmi_to_Ulpi(hdlName: str | None = None)[source]¶

Bases: HwModule

The ULPI is an interface which reduces the number of signals for UTMI+ interface. This reduction is done using a register file which drives signals which are not used and bi-directional wiring. This component does translation of ULPI to UTMI+ by keeping copy of UTMI+ registers and synchronizing the changes and it also handles the drive of the bi-directional wires.

Based on https://raw.githubusercontent.com/ultraembedded/core_ulpi_wrapper/3c202963ac4b4ae50cadb44ce79c11463d3c6484/src_v/ulpi_wrapper.v

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE
utmi - of type hwtLib.peripheral.usb.usb2.utmi.Utmi_8b - MASTER
ulpi - of type hwtLib.peripheral.usb.usb2.ulpi.Ulpi - SLAVE

schematic

__annotations__ = {}¶

static parse_RX_CMD(ulpi_data, utmi_linestate_q, utmi_interrupt_q, utmi_rxactive_q, utmi_rxerror_q)[source]¶

ulpi_turnaround_detect(ulpi_dir: RtlSignal)[source]¶

hwtLib.peripheral.usb.usb2.utmi_usb_agent module¶

class hwtLib.peripheral.usb.usb2.utmi_usb_agent.UtmiUsbAgent(sim: HdlSimulator, hwIO: Utmi_8bAgent, allowNoReset=False)[source]¶

Bases: Utmi_8bAgent, SyncAgentBase

:class:` hwtLib.peripheral.usb.usb2.utmi_agent.Utmi_8bAgent` with device host logic and USB stack

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO: Utmi_8bAgent, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶: Implement this method to drive your interface in simulation/verification

driver_init()[source]¶

getDrivers()[source]¶

Note:: use only before running simulator

getMonitors()[source]¶

Note:: use only before running simulator

monitor()[source]¶: Implement this method to monitor your interface in simulation/verification

monitor_init()[source]¶

run_usb_driver()[source]¶

class hwtLib.peripheral.usb.usb2.utmi_usb_agent.UtmiUsbDevProcAgent(rx: Deque[UsbPacketToken | UsbPacketData], tx: Deque[UsbPacketToken | UsbPacketData], descriptors: UsbDescriptorBundle)[source]¶

Bases: UsbDevAgent

__annotations__ = {}¶

deparse_packet(p)[source]¶: Called to convert the packet from types supported by this class before putting into tx/rx queue

parse_packet(p)[source]¶: Called to convert the packet from tx/rx queues to types supported by this class

parse_packet_pid_and_bytes(pid: int, p: Deque[int])[source]¶

class hwtLib.peripheral.usb.usb2.utmi_usb_agent.UtmiUsbHostProcAgent(rx: Deque[UsbPacketToken | UsbPacketData | UsbPacketHandshake], tx: Deque[UsbPacketToken | UsbPacketData | UsbPacketHandshake])[source]¶

Bases: UsbHostAgent

A simulation agent for hwtLib.peripheral.usb.usb2.utmi.Utmi_8b interface with the functionality of the host.

__annotations__ = {}¶

deparse_packet(p: UsbPacketToken | UsbPacketData | UsbPacketHandshake)[source]¶: Called to convert the packet from types supported by this class before putting into tx/rx queue

parse_packet(p: Deque[int])[source]¶: Called to convert the packet from tx/rx queues to types supported by this class

parse_packet_pid_and_bytes(pid: int, p: Deque[int])[source]¶

usb_packet_token_t = struct { <HBits, 4bits> pid <HBits, 4bits> pid_inv <HBits, 7bits> addr <HBits, 4bits> endp <HBits, 5bits> crc5 }¶